1. Field of the Invention
The present invention relates to a technique for designing a semiconductor integrated circuit. In particular, the present invention relates to a technique for designing a semiconductor integrated circuit based on a clock gating method.
2. Description of Related Art
An LSI has to meet “timing constraint” in order for the LSI to operate normally at a desired clock frequency. The timing constraint includes so-called “hold constraint” and “setup constraint”. For example, let us consider a case where a signal output from a first flip-flop is input to a second flip-flop. In this case, the timing at which the signal arrives at the second flip-flop is required to be after an input of the current clock and before an input of the next clock. Constraint relating to the former is the hold constraint, while constraint relating to the latter is the setup constraint.
In designing an LSI, it is necessary to design and optimize timing such that the above-mentioned timing constraint is met. Therefore, a timing analysis is important. In the timing analysis, circuit delays are estimated and whether or not each signal on each path meets the timing constraint is verified. However, the paths within the design target circuit include some paths that need not meet the usual timing constraint. Such a path is referred to as a “timing exception path”. The timing exception path includes a “false path” and a “multi-cycle path”.
The false path is a path through which a signal does not propagate logically. For example, in a case where one input of an AND gate is fixed to the logical value “0” in an actual operation of the LSI, a change in another input of the AND gate does not propagate to the subsequent stage. Therefore, an output path of the AND gate is the false path. Such false paths can be ignored in the timing analysis.
The multi-cycle path is a path through which a signal is allowed to take two or more clock cycles to propagate (refer to Japanese Laid Open Patent Application JP-P2004-171149A). For example, in a case where the LSI normally operates even when a signal takes 3 clock cycles to propagate through a certain path, the certain path is referred to as a “multi-cycle path of 3 cycles”. It is usually necessary to set a delay in a path of a combinational circuit section within one clock cycle. As for a multi-cycle path of n cycles (n is an integer not less than 2), however, it is possible to ease (relax) the timing constraint to be n clock cycles.
In recent years, the timing constraint has become more severe with speeding up and increasing miniaturization of the LSI. This leads to increase in time required for the timing designing, namely, time required for the LSI designing. If one can utilize information on the above-mentioned timing exception in the timing designing, the timing constraint is eased and thus unnecessary timing optimization processing can be omitted. For that purpose, it is preferable to give constraint for the timing exception path (hereinafter referred to as “timing exception constraint”) in addition to the usual timing constraint with regard to usual paths. When the timing exception constraint is given, the timing constraint is eased as a whole. To consider the timing-exception is important from a viewpoint of promoting the efficiency of the LSI designing.
Also, a technique called “clock gating”, which contributes to reduction of electric power consumption, is known in the technical field of the LSI (refer to Japanese Laid Open Patent Application JP-A-Heisei, 11-149496 and Japanese Laid Open Patent Application JP-P2002-190528A, for example). According to the clock gating, clock supply to a circuit which operates based on the clock is cut off in a period during which the circuit needs not operate. For example, clock supply to a register is cut off in a period during which a value of the register needs not be rewritten. Consequently, signal transition is stopped during that period and hence the electric power consumption is reduced.
In order to achieve the clock gating, a “gating cell” is usually employed. FIG. 1 shows a configuration of a gating cell GC which is well-known to the public (for example, see FIG. 6 in the Japanese Laid Open Patent Application JP-P2002-190528A). The gating cell GC shown in FIG. 1 is provided with an AND gate and a latch circuit. The latch circuit latches an enable signal en in synchronization with a clock signal clk. An output of the latch circuit and the clock signal clk are input to the AND gate. The enable signal en is a signal for activating a target circuit (a flip-flop or the like) that is a target of the clock gating, and is generated by an enable logic.
Such a gating cell GC is provided on a clock line in the clock gating processing. An output of the AND gate is connected to the above-mentioned target circuit, and thus the supply of the clock signal clk to the target circuit is controlled by the gating cell GC. When the enable signal en is activated, the gating cell GC supplies the clock signal clk to the target circuit. On the other hand, when the enable signal en is deactivated, the gating cell GC cuts off the supply of the clock signal clk to the target circuit. As a result, the target circuit is deactivated and the electric power consumption is reduced.
It should be noted that the clock gating can be also realized by using only an AND logic between the enable signal en and the clock signal clk. The reason why the gating cell GC shown in FIG. 1 is provided with the latch circuit is as follows. If the enable signal en is unstable, it causes such a problem as a plurality of clock pulses (glitch) are generated when the necessary number of clock pulses should be one. In order to avoid such the problem, the latch circuit is added to the gating cell GC. The latch circuit captures a status of the enable signal en and holds the status until a clock pulse is generated completely. As a result, the output of the AND gate is stabilized. Such the gating cell GC provided with the latch circuit is referred to as a “latch-based gating cell”.
The gating cell is automatically inserted by a logic synthesis tool at a time of a logic synthesis. At the time of the logic synthesis, the above-mentioned timing analysis is executed. Here, let us consider a case where the gating cell GC (latch-based gating cell) shown in FIG. 1 is used. In this case, the timing analysis is also performed with respect to the gating cell GC, because the latch circuit is a sequential circuit that operates based on the clock signal clk. In a case when the enable signal en is a signal of the timing exception path, to additionally give the “timing exception constraint” for the gating cell GC may be preferable from a standpoint of easing the timing constraint.
However, the timing exception constraint is basically supposed to be given only for a register and a flip-flop, and the operation of giving the timing exception constraint for the gating cell GC as well is cumbersome and complicated. The reason is that the gating cell GC is automatically generated by the logic synthesis tool during the logic synthesis, when the timing analysis is executed. In order to give the timing exception constraint for the gating cell GC in advance of the logic synthesis, it is necessary to predict a name (instance name) that is given to the gating cell GC. However, the prediction is obviously difficult.
As described above, the operation of giving the timing exception constraint for the gating cell GC is difficult and complicated for a circuit designer. This cancels the effect due to the easing (relaxation) of the timing constraint, which eventually results in deterioration of the efficiency of circuit designing.